I noticed the following issues when running the testbench with Icarus
verilog on cygwin/windows.

Refer to file tb_ethernet.v, version 1.34 (the latest).

1. Line 2442, I had to change ETH_MIIRX_DATA to ETH_MIITX_DATA, since
we are trying to read back and verify a value written to ETH_MIITX_DATA.

2. In lines 4259 - 4261 I had to change the declarations to unsigned:

reg [31:0] i_data; // was integer i_data;
reg [31:0] i_length; // was integer i_length;
reg [31:0] tmp_len; // was integer tmp_len;

because expressions like

`MEMORY_BASE + i_length[1:0]

were causing sign extension if i_length was, for example, 3. This was
causing reads and writes to memory locations just below MEMORY_BASE.

With those changes, things are MUCH better, but subsequent tests still
fail like this:

Heading: MAC HALF DUPLEX FLOW TEST


***************************************************************************************

***************************************************************************************


*************************************************************************************
At time: 487283647
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND
RECEIVING FRM. AT 4 TX/RX BD (
10Mbps )
*FAILED* because
Transmit should NOT start more than 1 CLK after CarrierSense and
causing Collision


Does anyone have the fixes to make the testbench run on Icarus windows
under cygwin? Any information on how to fix this last problem would be
greatly appreciated. Does anyone still maintain the testbench?

Thanks,
Chuck Heller